Transistor level static noise analysis is extremely important, considering the technology scaling and performance demands of digital design. A known process divides the circuit under test into a set of sub-circuits, called “evaluation nodes” or “channel connected components” (CCC). Each evaluation node is separately analyzed for its ability to respond in the presence of capacitive coupling, charge-sharing, power supply noise, and injected noise.
As is generally known, injected noise is unintended voltage fluctuations that propagate to a sub-circuit's inputs and are subsequently propagated through the sub-circuit. Injected noise analysis is a significant piece of static analysis of the entire circuit that requires an in-situ simulation of the sub-circuit and patterns that precondition it for a worst-case response to noise. These simulations of the various possible input sensitizations can consume 35 to 45% of the total runtime and can cause the overall noise analysis process to take up to several days on large circuits. As time to market is a key consideration in this industry, design efficiency is extremely critical.
A known static noise analysis, e.g., macro level signal analysis (MLSA), relies on the simulation of each evaluation node or channel-connected-component (CCC) of a larger circuit to characterize the noise that propagates through a circuit when its inputs are stimulated with input noise voltage waveforms. These simulations are called injected-noise simulations. Other types of noise to be analyzed can include coupling noise; charge sharing noise; and power supply noise.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.